A flash memory is widely used as a semiconductor memory. A flash memory utilizes a memory cell that belongs to a type of accumulating a charge in a floating gate. A Flash memory is widely used because it is a non-volatile device, as well as it provides a lower cost per 1-bit data and it can be highly integrated. Among others, a NAND flash memory can be particularly highly integrated because it includes a plurality of memory cells connected in series between select transistors, thereby providing fewer contacts between the memory cells. A multi-level storage product has been available that stores 2-bit or more data per one memory cell. Such a product can also provide a higher storage capacity, a lower cost, and a smaller space.
A data write operation (program operation) of the NAND flash memory requires a verify read operation to confirm whether the targeted threshold voltage is provided. If the verify read operation determines that the write is not sufficiently performed to the desired threshold voltage, the write voltage is stepwise raised (“a step-up operation”) and then similar write and verify read operations are repeated until the desired threshold voltage is provided.
In a highly integrated flash memory having scaled-down cells, interference between adjacent memory cells affects the threshold voltage distribution of the memory cell, such as increasing the distribution width and entirely moving the distribution. Particularly, the multi-level storage scheme requires setting of a smaller width of the threshold voltage distributions and a smaller distance between the threshold voltage distributions than in the case of the binary storage scheme. Accordingly, when the multi-level storage scheme is used, adjacent-cell interference may greatly affects on the data reliability. Various methods of data write have thus been proposed to minimize the affect of the adjacent-cell interference.
In order to provide a threshold voltage distribution having a smaller distribution width and a smaller distance between the threshold voltage distributions, it is usually effective to provide a smaller step-up width (an increase width) in the step-up operation. A smaller step-up width results in, however, a longer write time and reduced performance of the non-volatile semiconductor memory device. Accordingly, there is a need for a proposed non-volatile semiconductor memory device having a reduced write time while maintaining the data reliability.